On June 22 and 24, 2021 from 9:00 am to 12:30 pm PT each day, and again on June 29 and July 1, 2021 from 15:00 pm to 18:30 pm CET each day, Alliance Member company Seimens will deliver the virtual seminar “AI/ML Accelerator Tutorial: C-Level Design & Verification Using HLS”. From the event page:
Catapult HLS (High-Level Synthesis), C-level design and verification are reducing entire project development times by half or more in today’s ASIC and FPGA designs. It is being used to create production-quality HW Accelerators for multiple applications such as 5G, Communication, Image and Video Processing, Automotive, and AI/ML much faster than hand-coded RTL with equivalent PPA. Many new to HLS, however, have questions about how to take advantage of the productivity benefits of moving up in abstraction and still have the closure and confidence that they have with their current RTL verification methodology. This technical seminar will use an open-source AXI-based AI/ML accelerator example to step you through the entire flow from algorithm to verified RTL using HLS and HLV.
For more information and to register, visit the event page for the session of interest to you: