Lattice Semiconductor Demonstration of Random Bin Picking Based on Structured-Light 3D Scanning

Mark Hoopes, Senior Director of Industrial and Automotive at Lattice Semiconductor, demonstrates the company’s latest edge AI and vision technologies and products at the 2025 Embedded Vision Summit. Specifically, Hoopes demonstrates how Lattice FPGAs increase performance, reduce latency and jitter, and reduce overall power for a random bin picking robot.

The Lattice FPGA offloads the CPU by performing some of the control and processing steps – generation of the images, capturing the results, triangulating objects and generating the depth map. By offloading some of the processing to the low power Lattice FPGA, the system can be built using a less powerful and less costly CPU with cheaper, simpler cooling requirements. More details are provided in a white paper found here: https://www.latticesemi.com/view_document?document_id=54700.

Here you’ll find a wealth of practical technical insights and expert advice to help you bring AI and visual intelligence into your products without flying blind.

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