Highly scalable, area and power efficient machine learning accelerator core architecture.

January 4, 2023 – A critical requirement for the next wave of edge applications is advanced processing and machine learning capabilities. Machine learning use cases vary widely for the different markets and application domains requiring different amounts of acceleration compute performance and at differing amounts of power dissipation and overall solution cost.

One of the most effective ways to offer improved compute performance and power efficiency for machine learning applications is to integrate a purpose-built and dedicated neural processing unit (NPU), sometimes also referred to as a machine learning accelerator (MLA) or deep learning accelerators (DLA), into the device to complement the CPU compute cores.

NXP offers a very wide portfolio of devices from traditional MCUs in the Kinetis, LPC families and more recently the MCX portfolio of devices, to our i.MX RT crossover MCUs and our i.MX applications processors, and in each of the market areas we serve, we see an increased demand for efficient machine learning compute capabilities. To offer highly- optimized devices to our users across our portfolio, we developed the eIQ Neutron neural processing unit (NPU). The eIQ Neutron NPU architecture scales from the most efficient MCU to the most capable i.MX applications processors in our portfolio. This billions (Giga) to trillions (Tera) operations per cycle scalability combined with the support for a wide variety of neural network types such as CNN, RNN, TCN and Transformer networks and more is a recipe for success.

Figure 1: eIQ Neutron NPU block diagram

The eIQ Neutron NPU offers a rich set of options that can be leveraged based on the NXP edge processing device the core is integrated into and the market needs that device family is addressing.

  • Dedicated controller core
  • In-line dequantization, activation and pooling
  • Built in tiny-caching to reduce power consumption and reduce reliance on system memory speed
  • Weight decompression engine
  • Advanced multi-dimensional DMA for input and output formats, including striding, batching, interleaving, concatenating
  • Configurable coupled memory

Further to the hardware capabilities and features, the eIQ Neutron NPU cores are fully supported by the award winning eIQ® machine learning software development environment.

The combination of NXP developed hardware acceleration and software enablement offers our users the ability to leverage their experience across the NXP edge processing portfolio as well as the reassurance that support for emerging machine learning neural networks, models and operators can be more efficiently supported even after devices are deployed and in the field.

You can start to develop intelligent solutions with the eIQ Neutron NPU with the MCX-N series of MCUs and the i.MX 95 applications processors with more devices to come.

Explore eIQ Neutron NPU on MCX N MCUs:

i.MX 95 Family of Applications Processors:

Ali Ors
Director, AI ML Strategy and Technologies, Edge Processing, NXP Semiconductors

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