Andes Technology

10xEngineers and Andes Enable High-Performance AI Compilation for RISC-V AX46MPV Cores

Algorithms & Models, Andes Technology, News, Processors /

Hsinchu, Taiwan – February 26, 2026 – The collaboration between 10xEngineers, a services company specializing in AI compilers, and Andes Technology Corporation, a leading provider of high-performance, low-power 32- and 64-bit RISC-V processor IP and a Founding Premier Member of RISC-V International, delivers first-class AI workload compilation for Andes AX46MPV cores using 10xEngineers’ AI graph compiler, Baltoro. This collaboration enables […]

10xEngineers and Andes Enable High-Performance AI Compilation for RISC-V AX46MPV Cores Read More +

Andes Showcases Expanding RISC-V Ecosystem and Next-generation “Cuzco” High-performance CPU at RISC-V Summit North America 2025

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San Jose, CA October 17, 2025 –– Andes Technology, a Founding Premier Member of RISC-V International and a leading supplier of high-efficiency, high-performance RISC-V processor IPs, will highlight its expanding ecosystem and preview its next-generation out-of-order CPU—code-named “Cuzco”—at RISC-V Summit North America 2025, taking place October 22–23 in Santa Clara, California. Building on its success in

Andes Showcases Expanding RISC-V Ecosystem and Next-generation “Cuzco” High-performance CPU at RISC-V Summit North America 2025 Read More +

Andes Technology Expands Comprehensive AndeSentry Security Suite with Complete Trusted Execution Environment Support for Embedded Systems

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Includes IOPMP, Secure Boot, MCU-TEE for RTOS, and OP-TEE for Linux to Protect Devices from MCUs to Edge AI Processors Hsinchu, Taiwan – October 6th, 2025 – Andes Technology Corporation, the leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores, today announced the latest AndeSentry™ Framework with two new components, Secure Boot v1.0.1 and MCU-TEE

Andes Technology Expands Comprehensive AndeSentry Security Suite with Complete Trusted Execution Environment Support for Embedded Systems Read More +

2025 Andes RISC-V CON Debuts in Seoul

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Showcasing AI and Automotive Solutions Powered by RISC-V September 12, 2025 – Seoul, South Korea – As AI and automotive systems evolve at unprecedented speed, engineers are seeking more flexible, efficient, and secure computing solutions. RISC-V, with its open and extensible architecture, is fast becoming the preferred foundation for next-generation SoC designs. To explore this

2025 Andes RISC-V CON Debuts in Seoul Read More +

Andes Technology Announces D23-SE: A Functional Safety RISC-V Core with DCLS and Split-lock for ASIL-B/D Automotive Applications

Andes Technology, Automotive, News, Processors /

Hsinchu, Taiwan – September 03, 2025 – Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores, today announced the launch of its new D23-SE core, a compact and secure processor designed for functional safety applications. Based on the production-proven D23, the D23-SE is engineered to meet the stringent safety and performance requirements of

Andes Technology Announces D23-SE: A Functional Safety RISC-V Core with DCLS and Split-lock for ASIL-B/D Automotive Applications Read More +

Andes Technology Further Expands Long-term Collaboration with Sequans Communications with AndesCore A25MP and N25F RISC-V CPU Core Licenses

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Hsinchu Science Park, Taiwan – August 28th, 2025 – Andes Technology Corporation (TWSE: 6533) today celebrated ten years of collaboration with Sequans Communications, with the latest licensing of Andes’ A25MP and N25F RISC-V CPU intellectual property (IP) cores for Sequans’ next-generation Internet of Things (IoT) chipsets featuring 4G and 5G eRedCap cellular network technologies. Sequans, a fabless

Andes Technology Further Expands Long-term Collaboration with Sequans Communications with AndesCore A25MP and N25F RISC-V CPU Core Licenses Read More +

Andes Technology’s AutoOpTune Applies Genetic Algorithms to Accelerate RISC-V Software Optimization

Algorithms & Models, Andes Technology, News, Processors, Software, Tools /

Andes AutoOpTune™ v1.0 accelerates software development by giving software developers the ability to automatically explore and choose the compiler optimizations to achieve their performance and code-size targets. Hsinchu, Taiwan – July 10, 2025 – Andes Technology, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, today

Andes Technology’s AutoOpTune Applies Genetic Algorithms to Accelerate RISC-V Software Optimization Read More +

Andes Technology Advances High-performance RISC-V Strategy with U.S.-based Design Center: Condor Computing

Andes Technology, News, Processors /

San Jose, CA – July 7, 2025 – Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), the leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announced a major milestone in its U.S. expansion through Condor Computing, a wholly owned subsidiary based in Austin, Texas. Condor Computing was established

Andes Technology Advances High-performance RISC-V Strategy with U.S.-based Design Center: Condor Computing Read More +

Andes Technology Unveils AndesAIRE AnDLA I370: A Next-generation Deep Learning Accelerator for Edge and Endpoint AI

Andes Technology, News, Processors, Tools /

Hsinchu, Taiwan –June 05, 2025 – Andes Technology, a leading supplier of high-performance, low-power 32/64-bit RISC-V processor cores and AI acceleration solutions, proudly announces the launch of AndesAIRE™ AnDLA™ I370, its latest Deep Learning Accelerator (DLA), engineered to bring advanced neural network performance to cost-sensitive edge and endpoint AI applications. Building on the success of

Andes Technology Unveils AndesAIRE AnDLA I370: A Next-generation Deep Learning Accelerator for Edge and Endpoint AI Read More +

Andes Technology, Baya Systems and Imagination Technologies to Present on Heterogeneous Compute Architectures at Andes RISC-V CON Silicon Valley

Andes Technology, Imagination Technologies, News, Processors /

Technical session to explore memory hierarchy, CPU-GPU interaction and real-world integration strategies for accelerating AI and edge workloads SANTA CLARA, CA – April 24, 2025 – Baya Systems, a leader in high-performance system architecture and design tools, today announced it will participate in Andes RISC-V CON Silicon Valley. In a joint developer track session with

Andes Technology, Baya Systems and Imagination Technologies to Present on Heterogeneous Compute Architectures at Andes RISC-V CON Silicon Valley Read More +

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Berkeley Design Technology, Inc.
PO Box #4446
Walnut Creek, CA 94596

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