On July 29, 2026 at 10:00 am PT (1:00 pm ET), Intel will present the webinar “Agentic Smart City Systems: Real-Time Traffic Orchestration.” Here’s the description, from the event registration page: Beat congestion, save time, and route smarter in this hands-on, gamified workshop where Agentic AI meets Edge AI to power next-generation smart cities and […]
Upcoming Webinar on Agentic Smart City Systems Read More +
Beyond TOPS: The First Full-Pipeline AI Vision Benchmark EdgeFirst Perception Index profiles the entire perception pipeline — from CoreML to CUDA, desktop GPU to sub-7-watt edge NPU — and is the first independent benchmark to validate YOLO26 on edge hardware. The Q2 edition includes 330+ full validation sessions of 4 Ultralytics YOLO model families (21
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Lattice Semiconductor demonstrates a complete end-to-end vision pipeline running entirely on an FPGA, from CSI camera input to screen output. Raw sensor data is processed by an on-chip ISP that converts it to a clean YUV 422 video stream in real time. The platform includes a dedicated ISP builder and tuning tool, allowing designers to
Lattice FPGA Embedded Vision: Real-Time ISP Pipeline with Integrated Tuning Tool Read More +
Tecphos demonstrates real-time video over Ethernet using a Lattice CrossLink-NX 40 FPGA at the Embedded Vision Summit. The FPGA captures raw image data from a MIPI image sensor, processes and scales it, and simultaneously delivers an uncompressed stream to the host while compressing it to JPEG on-chip. Compressed data is formatted into Ethernet packets and
Video over Ethernet on Lattice CrossLink™-NX FPGA: Microsecond Latency Demo Read More +
This blog post was originally published at e-con Systems’ website. It is reprinted here with the permission of e-con Systems. When discussing 3D depth cameras, “high-resolution” refers to a sensor’s ability to capture a dense, detailed map of distance measurements. Specifically, it means the sensor provides more individual data points, or pixels, across its field of
Why High-Resolution 3D Depth Is Critical for Next-Generation Robots Read More +
Mark Oliver, the VP of Marketing at Efinix demonstrates how multiple AI models can be compiled to run on dedicated AI accelerators implemented in the high performance Titanium FPGA family. He shows how Efinix supplied tools can be used to optimize an AI model to run on an AI accelerator delivering hardware level performance while
Mark Oliver, the VP of Marketing at Efinix demonstrates the ability to run four independent AI models on the hardened quad core processor inside the Titanium family of FPGAs. He shows how an intuitive software flow can be accelerated through custom instructions to run “bottle neck” software routines in the FPGA fabric at hardware speed
Mark Oliver Demonstrates the Power of Custom Instruction Acceleration for Edge AI Read More +
This blog post was originally published at Samsung Semiconductor’s website. It is reprinted here with the permission of Samsung Semiconductor. Smartphone cameras have evolved far beyond simple tools for capturing moments. Today, users want to frame an entire landscape during travel, then zoom in to clearly see the windows of a distant building. Whether shooting in
What Defines a True 200-Megapixel Experience? Read More +
Mark Oliver, the VP or Marketing at Efinix demonstrates the superior performance of an AI algorithm to perform super resolution on a low resolution image. This approach is only feasible due to the low power consumption and superior performance of the Efinix Titanium family of FPGAs meaning that the super resolution functionality can be placed
Mark Oliver Demonstrates Super Resolution on the Power-Efficient Efinix Titanium FPGAs Read More +
This demonstration by MosChip and Cadence shows a Small Language Model (SLM) voice assistant running entirely on-device on the Cadence Tensilica Vision Q7 DSP within an Axera AX650N platform – with no cloud connection. It walks through the full interaction loop: spoken input is converted to text, a compact quantized language model (SLM) generates
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