Cadence Accelerates On-device and Edge AI Performance and Efficiency with New Neo NPU IP and NeuroWeave SDK for Silicon Design
Highlights: Neo NPUs efficiently offload from any host processor and scale from 8 GOPS to 80 TOPS in a single core, extending to hundreds of TOPS for multicore AI IP delivers industry-leading AI performance and energy efficiency for optimal PPA and cost points Targets a broad range of on-device and edge applications, including intelligent sensors, […]