This blog post was originally published at Qualcomm’s website. It is reprinted here with the permission of Qualcomm. “It’s amazing how Qualcomm was able to turn the ship on a dime since the last [Embedded World] show. The launch of Qualcomm Dragonwing and the Partner Day event were on point and helpful, showing Qualcomm’s commitment […]
Qualcomm Trends and Technologies to Watch In IoT and Edge AI Read More +
Yair Siegel, Senior Director for Wireless and Emerging Markets at Ceva, presents the “NPU IP Hardware Shaped Through Software and Use-case Analysis” tutorial at the May 2025 Embedded Vision Summit. True innovation in tiny machine learning (tinyML) emerges from a synergy between software ingenuity, real-world application insights and leading-edge processor IP. In this presentation, Siegel
AI model optimization powers high-efficiency DMS on ultra-compact MCUs 50FPS real-time performance with ultra-low power and minimal system footprint SEOUL, South Korea, July 2, 2025 /PRNewswire/ — Nota AI, a global leader in AI optimization, today announced a collaboration with Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, to deliver an optimized Driver Monitoring
Pete Warden, CEO of Useful Sensors, presents the “Voice Interfaces on a Budget: Building Real-time Speech Recognition on Low-cost Hardware” tutorial at the May 2025 Embedded Vision Summit. In this talk, Warden presents Moonshine, a speech-to-text model that outperforms OpenAI’s Whisper by a factor of five in terms of speed. Leveraging this efficiency, he shows
Advanced Professional Video CODEC from Chips&Media is now on its way to the Android industry to enable extreme image quality as well as professional video experience in capture, playback, and edit use-cases in APV ecosystem. Key notes: New CODEC for professional video experience, in healthy competition with ProRes in iOS Ideal for edge devices even
Chips&Media’s New APV CODEC Delivers Extreme Visual Quality to the Android Industry Read More +
Single- and Dual-Core MCUs Combine Arm Cortex-M85 and M33 Cores with Arm Ethos-U55 NPU to Deliver Superior AI Performance up to 256 GOPs Unprecedented 7300+ CoreMarks[1] with Dual Arm CPU cores TSMC 22ULL Process Delivers High Performance and Low Power Consumption Embedded MRAM with Faster Write Speeds and Higher Endurance and Retention Dedicated Peripherals Optimized
Renesas Sets New MCU Performance Bar with 1-GHz RA8P1 Devices with AI Acceleration Read More +
Edge AI was the primary focus of microcontroller vendors at the 2025 Embedded World Exhibition. We caught up with some industry executives for our annual Embedded Quest program, asking them about their take on Edge AI. As usual, the Embedded World Exhibition in Nuremberg, Germany, drew a large crowd of companies in the computing processor
Embedded Quest 2025: MCU Vendors Step up Edge AI Play Read More +
This blog post was originally published at NVIDIA’s website. It is reprinted here with the permission of NVIDIA. To get the most out of AI, optimizations are critical. When developers think about optimizing AI models for inference, model compression techniques—such as quantization, distillation, and pruning—typically come to mind. The most common of the three, without
Introducing NVFP4 for Efficient and Accurate Low-precision Inference Read More +
This blog post was originally published at Renesas’ website. It is reprinted here with the permission of Renesas. Edge AI is no longer a futuristic idea—it’s an essential technology driving today’s smart devices across industries, from industrial automation to consumer IoT applications. But building AI applications at the edge still comes with challenges: complexity with
Simplifying Vision AI Development with Renesas AI Model Deployer Powered by NVIDIA TAO Read More +
Nigel Drego, Co-founder and Chief Technology Officer at Quadric, presents the “ONNX and Python to C++: State-of-the-art Graph Compilation” tutorial at the May 2025 Embedded Vision Summit. Quadric’s Chimera general-purpose neural processor executes complete AI/ML graphs—all layers, including pre- and post-processing functions traditionally run on separate DSP processors. To enable this, the Chimera Graph Compiler
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