This blog post was originally published at NVIDIA’s website. It is reprinted here with the permission of NVIDIA. Conservationists have launched a new AI tool that can sift through petabytes of underwater imaging from anywhere in the world to identify signs of abandoned or lost fishing nets—so-called ghost nets. Each year, around 2% of the […]
AI Helps Locate Dangerous Fishing Nets Lost at Sea Read More +
The energy-efficient architecture scales across AI-enabled devices, including AI phones and AI PCs Shanghai, China, June 9, 2025–VeriSilicon (688521.SH) today announced that its ultra-low energy and high-performance Neural Network Processing Unit (NPU) IP now supports on-device inference of large language models (LLMs) with AI computing performance scaling beyond 40 TOPS. This energy-efficient NPU architecture is
Provide AI acceleration with high computing density, multi-chip scaling, and 3D-stacked memory integration Shanghai, China, June 9, 2025–VeriSilicon (688521.SH) today announced the latest advancements in its high-performance and scalable GPGPU-AI computing IPs, which are now empowering next-generation automotive electronics and edge server applications. Combining programmable parallel computing with a dedicated Artificial Intelligence (AI) accelerator, these
Providing architecture design, software-hardware co-development, and mass production support, and enhancing AI-powered imaging capabilities in smart devices Shanghai, China, June 9, 2025–VeriSilicon (688521.SH) recently announced that its AI-ISP custom chip solution has been successfully adopted in a customer’s mass-produced smartphones, reaffirming the company’s comprehensive one-stop custom silicon service capabilities in AI vision processing. VeriSilicon’s AI-ISP
Now available for free download from Alliance Member company The SHD Group is their latest market report, Edge AI Market Analysis: Applications, Processors and Ecosystem Guide, developed in partnership with the Edge AI and Vision Alliance. The report provides a detailed exploration of the rapidly evolving edge AI landscape, covering critical insights on emerging applications,
The SHD Group Releases New Edge AI Processor and Ecosystem Report Read More +
Sreepada Hegade, Director of ML Systems and Software at Lattice Semiconductor, presents the “Why It’s Critical to Have an Integrated Development Methodology for Edge AI” tutorial at the May 2025 Embedded Vision Summit. The deployment of neural networks near sensors brings well-known advantages such as lower latency, privacy and reduced overall system cost—but also brings
Amol Borkar, Product Marketing Director at Cadence, presents the “Solving Tomorrow’s AI Problems Today with Cadence’s Newest Processor” tutorial at the May 2025 Embedded Vision Summit. Artificial intelligence is rapidly integrating into every aspect of technology. While the neural processing unit (NPU) often receives the majority of the spotlight as the ultimate AI problem solver,
Hsinchu, Taiwan –June 05, 2025 – Andes Technology, a leading supplier of high-performance, low-power 32/64-bit RISC-V processor cores and AI acceleration solutions, proudly announces the launch of AndesAIRE™ AnDLA™ I370, its latest Deep Learning Accelerator (DLA), engineered to bring advanced neural network performance to cost-sensitive edge and endpoint AI applications. Building on the success of
2025-06-05 – Chips&Media unveiled WAVE-N that is a custom NPU designed to work with imaging application at high-quality and high-resolution for edge device market at Embedded Vision Summit 2025 in Santa Clara San Jose, California. Key notes Extreme efficiency, up to 90% of MAC utilization, for Modern CNN Computation Highly optimized for real-time video processing
Chips&Media Unveils WAVE-N: A Custom NPU for High-quality, High-resolution Imaging Read More +
Tony Lewis, Chief Technology Officer at BrainChip, presents the “State-space Models vs. Transformers for Ultra-low-power Edge AI” tutorial at the May 2025 Embedded Vision Summit. At the embedded edge, choices of language model architectures have profound implications on the ability to meet demanding performance, latency and energy efficiency requirements. In this presentation, Lewis contrasts state-space
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